Work on the miniaturization of process technology has been proceeding in order to further increase the packing density of semiconductor devices. As the feature sizes of semiconductor devices decrease, interconnect structures for connecting the devices to each other have also been decreasing in size.
Furthermore, for semiconductor devices, not only the need for higher packing density but also the need for lower power consumption, higher operating speed, etc., has been increasing, necessitating a reduction in the dielectric constant of inter-metal insulating layers.
As a technique for forming an interconnect structure to meet such needs, a damascene process is widely used which forms an embedded interconnect by embedding an electrical conductive material into a trench formed from a low dielectric constant material and removing excess conductive material by chemical mechanical polishing. In particular, a dual damascene process which simultaneously forms a via and an embedded interconnect has been attracting attention from the standpoint of simplifying the fabrication process.
FIGS. 1A to 1I illustrate one example of a related art fabrication process for forming an interconnect line by using a dual damascene process.
First, as depicted in FIG. 1A, a barrier layer 124, a first insulating layer 130, and a second insulating layer 131 are formed one on top of another on an interconnect layer 125 formed in a multilayer structure fabricated by stacking an insulating layer 122 and a silicon carbide layer 123. Further, a first hard mask layer 132 of silicon oxide is formed on top of the second insulating layer 131, and a second hard mask layer 133 of silicon nitride is formed on top of the first hard mask layer 132.
Subsequently, a via 135 is formed in a region above the interconnect layer 125 by passing through the second hard mask layer 133, the first hard mask layer 132, the second insulating layer 131, and the first insulating layer 130.
Next, as depicted in FIG. 1B, a first resist layer 140 is formed in such a manner as to fill the via 135 and to cover the second hard mask layer 133.
Next, as depicted in FIG. 1C, the first resist layer 140 is etched back until the second hard mask layer 133 is exposed, and the upper surface of the first resist layer 140 is planarized so that it becomes coplanar with the upper surface of the second hard mask layer 133.
Next, as depicted in FIG. 1D, a BARC (Bottom Anti-Reflective Coating) layer 141 and a second resist layer 142 are formed on top of the second hard mask layer 133. Subsequently, an opening 150 for forming an interconnect groove is formed by patterning the second resist layer 142 in such a manner to be aligned with the via 135.
Next, as depicted in FIG. 1E, using the patterned second resist layer 142 as a mask, the BARC layer 141 and the second hard mask layer 133 are etched until the first mask layer 132 is exposed, and the second hard mask layer 133 is thus patterned.
Next, as depicted in FIG. 1F, the second resist layer 142, the BARC layer 141, and the first resist layer 140 embedded in the via 135 are removed by asking.
Next, as depicted in FIG. 1G, using the patterned second hard mask layer 133 as a mask, the first hard mask layer 132 is etched, and the first hard mask layer 132 is thus patterned.
Next, as depicted in FIG. 1H, using the second hard mask layer 133 and first hard mask layer 132 as a mask, the second insulating layer 131 is etched until the first insulating layer 130 is exposed, and an interconnect groove 136 is formed in the second insulating layer 131. With this etching, not only is the second hard mask layer 133 removed, but also the thickness of the first hard mask layer 132 is reduced by etching. Further, with this etching, the portion of the barrier layer 124 that is exposed in the via 135 is removed, and the interconnect layer 125 is exposed in the via 135.
Finally, as depicted in FIG. 1I, an electrically conductive material 137 is embedded into the via 135 and the interconnect groove 136, thus forming an embedded interconnect layer 138 in the second insulating layer 131.
Another example of a related art fabrication process for forming an interconnect line by using the dual damascene process will be described with reference to FIGS. 2A and 2B.
First, the structure depicted in FIG. 1E is formed by performing the same processing as described above.
Next, as depicted in FIG. 2A, using the second resist layer 142 as a mask, the first hard mask layer 132 is etched to form a pattern in the first hard mask layer 132. The first and second resist layers 140 and 142 are not yet removed by ashing.
Next, as depicted in FIG. 2B, the first resist layer 140, the second resist layer 142, and the BARC layer 141 are removed by ashing, after which the interconnect is formed by performing the same fabrication steps as those depicted in FIGS. 1G to 1I.
In the interconnect formation method illustrated in FIGS. 1A to 1I, provision has to be made so that the second hard mask layer 133 acting as a mask will not be etched away when etching the first hard mask layer 132 in the step of FIG. 1G. For this purpose, it is necessary to use an etching gas that etches the first hard mask layer 132 at a greater rate than the second hard mask layer 133. Since the etching gas needs to have etching selectivity, such that the etching rate is greater for the first hard mask layer 132 than for the second hard mask layer 133, the types of etching gases that can be used are limited. This limits the freedom in the process.
On the other hand, in the interconnect formation method illustrated in FIGS. 2A and 2B, since the first hard mask layer 132 is etched while leaving the second resist layer 142 on the second hard mask layer 133, the second hard mask layer 133 can be prevented from being etched. However, since the first hard mask layer 132 is etched while leaving the first resist layer 140 unremoved, deposits containing etching by-products may accumulate on the sidewalls of the first resist layer 140 and may be left as fences 160 after removing the first resist layer 140, as depicted in FIGS. 2A and 2B.
Japanese Laid-open Patent Publication No. 2001-77196
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